1. Technical Field
The invention relates to computer processor units and, more particularly, to reconstructing the address of the next instruction to be completed in pipelined computer processing units.
2. Description of the Prior Art
Pipelined processors divide the processing of instructions into a number of stages such that several instructions can be processed simultaneously, thereby providing improved efficiency and performance with respect to conventional non-pipelined processors. More recently superscalar processors, such as the Pentium processor from Intel and the PowerPC 601, 603, 604 and 620 processors from Apple/IBM/Motorola have been developed that utilize multiple instruction pipelines to provide the ability to execute multiple instructions in a single clock cycle. Thus, superscalar and pipelined microprocessors process a large number of instructions concurrently.
As shown in FIG. 1, the structure of these devices typically may be broken down into four stages. In the fetch stage, a copy of one or more instructions are obtained from memory and placed into an input queue. In the dispatch stage, one or more instructions are read from the input queue and examined to initialize the control signals that are required for execution, and then dispatched to the execution unit(s). In the execution stage, when resources are available, one or more instructions are executed. Finally, in the completion stage, the results produced by the execution unit(s) are committed to the architected registers.
The instructions are typically fetched and dispatched in order, but may be executed out of order. In order to give the illusion of a traditional sequential machine, the instructions are finally reordered at completion time. Such an architecture has the advantage of decoupling instruction fetch from execution, thus providing higher performance.
In addition, branch prediction and prefetch control logic may be utilized to fetch, dispatch and execute instructions speculatively. However, these speculative instructions are not completed until the speculative conditions have been resolved. Such speculative fetching and execution also improves system performance in most applications.
Microprocessors that incorporate the structure of FIG. 1 typically include a program counter that stores the memory address of the last instruction completed by the completion stage such that the microprocessor can service interrupts and/or program exceptions. Upon experiencing an interrupt/exception, the current address of the program counter is saved. The program counter is then initialized with an address vector corresponding to the interrupt/exception and the instruction pipeline reset for fetching, dispatching, executing and completing the instructions of the interrupt/exception. To return from the interrupt/exception, the stored address value (or the next sequential address following the stored address value) is loaded into the program counter and the instruction pipeline is reset for fetching, dispatching, executing and completing the instruction sequence that the microprocessor left to service the interrupt/exception.
Conventionally, the program counter is implemented by saving the full address of each instruction in the fetch stage, and writing the full address+1 or target address to the program counter upon completing the instruction. However, this implementation may be unsuitable for use in superscalar and deeply pipelined microprocessors that process a large number of instructions concurrently. In these applications, storing the full address of each instruction requires that a large amount of information be stored, and thus may consume an unacceptable amount of real estate.
It is therefore an object of the present invention to provide a system that utilizes a limited amount of stored information and a small amount of real estate to perform the conventional functions of the program counter, and is thus suitable for use in superscalar and pipelined microprocessors.